
芯片 | CC3200 | RAM | 256KB(200KB) |
尺寸 | 20.5*17.5 mm | Flash | 1MB (MAX:16MB) |
天線 | 無 | 接口 | UART/GPIO/SPI |
透傳與AT指令 | 無 | 內核 | Cortex-M4(32bits) |
協議 | 802.11 b/g/n | 工作頻段 | 2400~2483.5MHz |
引出IO數 | 28 | 頻段 | 2.4 GHz |
功耗 | 模式0: 74mA 模式1: 20mA 模式2: 1.5mA 模式3: 35μA |
傳輸速率 | SPI-WiFi: 400KB/S WiFi: 800KB/S |
實測功耗
從不以理論值代替實際值宣傳

模塊可在STA模式建立TCP連接
作為Client與遠端服務器連接通信

模塊可在STA模式建立TCP Server
并與其他Internet設備連接通信

模塊可在AP模式建立TCP Server
其他Wi-Fi設備在STA模式TCP Client與之相互通信

原廠可替換
可直接替換原廠CC3200MOD

支持低功耗
優化后可以將Wi-Fi節點的續航提升至12個月

實測距離
在天氣晴朗 空曠可視 距地約為2米的郊區進行測試

高低溫
能夠適應各種惡劣環境

寬電壓
更寬的電壓適用范圍

應用場景

引腳圖

腳位 | 名稱 | 功能 | 備注­­ |
Pin1 | GND | - | Ground |
Pin2 | GND | - | Ground |
Pin3 | GPIO10 | I/O | GPIO |
Pin4 | GPIO11 | I/O | GPIO |
Pin5 | GPIO14 | I/O | GPIO |
Pin6 | GPIO15 | I/O | GPIO |
Pin7 | GPIO16 | I/O | GPIO |
Pin8 | GPIO17 | I/O | GPIO |
Pin9 | GPIO12 | I/O | GPIO |
Pin10 | GPIO13 | I/O | GPIO |
Pin11 | GPIO22 | I/O | GPIO |
Pin12 | JTAG_TDI | I/O | JTAG TDI input. Leave unconnected if not used on product |
Pin13 | FLASH_SPI_MISO | I | External Serial Flash Programming: SPI data in |
Pin14 | FLASH_SPI_nCS_IN | I | External Serial Flash Programming: SPI chip select (active low) |
Pin15 | FLASH_SPI_CLK | I | External Serial Flash Programming: SPI clock |
Pin16 | GND | - | Ground |
Pin17 | FLASH_SPI_MOSI | O | External Serial Flash Programming: SPI data out |
Pin18 | JTAG_TDO | I/O | JTAG TDO output. Leave unconnected if not used on product |
Pin19 | GPIO28 | I/O | GPIO |
Pin20 | NC | - | - |
Pin21 | JTAG_TCK | I/O | JTAG TCK input. Leave unconnected if not used on product.(2)
An internal 100 kΩ pull down resistor is tied to this pin. |
Pin22 | JTAG_TMS | - | JTAG TMS input. Leave unconnected if not used on product. |
Pin23 | SOP2 | - | An internal 100 kΩ pull down resistor is tied to this SOP pin. An
external 10 kΩ resistor is required to pull this pin high. See
Section 6.11.1 for SOP[2:0] configuration modes. |
Pin24 | SOP1 | - | An internal 100 kΩ pull down resistor is tied to this SOP pin. An
external 10 kΩ resistor is required to pull this pin high. See
Section 6.11.1 for SOP[2:0] configuration modes. |
Pin25 | GND | - | Ground |
Pin26 | GND | - | Ground |
Pin27 | GND | - | Ground |
Pin28 | GND | - | Ground |
Pin29 | GND | - | Ground |
Pin30 | GND | - | Ground |
Pin31 | RF_ABG | I/O | Ground |
Pin32 | GND | - | Ground |
Pin33 | NC | - | - |
Pin34 | SOP0 | | An internal 100 kΩ pull down resistor is tied to this SOP pin. An
external 10 kΩ resistor is required to pull this pin high. See
Section 6.11.1 for SOP[2:0] configuration modes. |
Pin35 | nRESET | I | There is an internal, 100 kΩ, pull-up resistor option from the
nRESET pin to VBAT_RESET. Note: VBAT_RESET is not
connected to VBAT1 or VBAT2 within the module. The following
connection schemes are recommended:
• Connect nRESET to a switch, external controller, or host,
only if nRESET will be in a defined state under all operating
conditions. Leave VBAT_RESET unconnected to save
power.
• If nRESET cannot be in a defined state under all operating
conditions, connect VBAT_RESET to the main module
power supply (VBAT1 and VBAT2). Due to the internal pullup
resistor a leakage current of 3.3 V / 100 kΩ is expected. |
Pin36 | VBAT_RESET | - |
Pin37 | VBAT1 | Power | Power supply for the module, must be connected to battery (2.3
V to 3.6 V) |
Pin38 | GND | - | Ground |
Pin39 | NC | - | - |
Pin40 | VBAT2 | Power | Power supply for the module, must be connected to battery (2.3
V to 3.6 V) |
Pin41 | NC | - | - |
Pin42 | GPIO30 | | GPIO |
Pin43 | GND | | Ground |
Pin44 | GPIO30 | | |
Pin45 | NC | - | - |
Pin46 | GPIO1 | I/O | GPIO |
Pin47 | GPIO2 | I/O | GPIO |
Pin48 | GPIO3 | I/O | GPIO |
Pin49 | GPIO4 | I/O | GPIO |
Pin50 | GPIO5 | I/O | GPIO |
Pin51 | GPIO6 | I/O | GPIO |
Pin52 | GPIO7 | I/O | GPIO |
Pin53 | GPIO8 | I/O | GPIO |
Pin54 | GPIO9 | I/O | GPIO |
Pin55 | GND | - | Thermal ground |
Pin56 | GND | - | Thermal ground |
Pin57 | GND | - | Thermal ground |
Pin58 | GND | - | Thermal ground |
Pin59 | GND | - | Thermal ground |
Pin60 | GND | - | Thermal ground |
Pin61 | GND | - | Thermal ground |
Pin62 | GND | - | Thermal ground |
Pin63 | GND | - | Thermal ground |
設計·仿真
良好的性能來源于全局仿真介入
真正的好產品 都是“精打細算”設計而出,強大的設計能力才能做出好產品

設計·天線
天線是通信系統關鍵環節
好的天線是通信系統穩定的核心競爭力

實力認證
九年技術積累 領跑無線行業




機械尺寸

引腳定義

腳位 | 名稱 | 功能 | 備注­­ |
Pin1 | GND | - | Ground |
Pin2 | GND | - | Ground |
Pin3 | GPIO10 | I/O | GPIO |
Pin4 | GPIO11 | I/O | GPIO |
Pin5 | GPIO14 | I/O | GPIO |
Pin6 | GPIO15 | I/O | GPIO |
Pin7 | GPIO16 | I/O | GPIO |
Pin8 | GPIO17 | I/O | GPIO |
Pin9 | GPIO12 | I/O | GPIO |
Pin10 | GPIO13 | I/O | GPIO |
Pin11 | GPIO22 | I/O | GPIO |
Pin12 | JTAG_TDI | I/O | JTAG TDI input. Leave unconnected if not used on product |
Pin13 | FLASH_SPI_MISO | I | External Serial Flash Programming: SPI data in |
Pin14 | FLASH_SPI_nCS_IN | I | External Serial Flash Programming: SPI chip select (active low) |
Pin15 | FLASH_SPI_CLK | I | External Serial Flash Programming: SPI clock |
Pin16 | GND | - | Ground |
Pin17 | FLASH_SPI_MOSI | O | External Serial Flash Programming: SPI data out |
Pin18 | JTAG_TDO | I/O | JTAG TDO output. Leave unconnected if not used on product |
Pin19 | GPIO28 | I/O | GPIO |
Pin20 | NC | - | - |
Pin21 | JTAG_TCK | I/O | JTAG TCK input. Leave unconnected if not used on product.(2)
An internal 100 kΩ pull down resistor is tied to this pin. |
Pin22 | JTAG_TMS | - | JTAG TMS input. Leave unconnected if not used on product. |
Pin23 | SOP2 | - | An internal 100 kΩ pull down resistor is tied to this SOP pin. An
external 10 kΩ resistor is required to pull this pin high. See
Section 6.11.1 for SOP[2:0] configuration modes. |
Pin24 | SOP1 | - | An internal 100 kΩ pull down resistor is tied to this SOP pin. An
external 10 kΩ resistor is required to pull this pin high. See
Section 6.11.1 for SOP[2:0] configuration modes. |
Pin25 | GND | - | Ground |
Pin26 | GND | - | Ground |
Pin27 | GND | - | Ground |
Pin28 | GND | - | Ground |
Pin29 | GND | - | Ground |
Pin30 | GND | - | Ground |
Pin31 | RF_ABG | I/O | Ground |
Pin32 | GND | - | Ground |
Pin33 | NC | - | - |
Pin34 | SOP0 | | An internal 100 kΩ pull down resistor is tied to this SOP pin. An
external 10 kΩ resistor is required to pull this pin high. See
Section 6.11.1 for SOP[2:0] configuration modes. |
Pin35 | nRESET | I | There is an internal, 100 kΩ, pull-up resistor option from the
nRESET pin to VBAT_RESET. Note: VBAT_RESET is not
connected to VBAT1 or VBAT2 within the module. The following
connection schemes are recommended:
• Connect nRESET to a switch, external controller, or host,
only if nRESET will be in a defined state under all operating
conditions. Leave VBAT_RESET unconnected to save
power.
• If nRESET cannot be in a defined state under all operating
conditions, connect VBAT_RESET to the main module
power supply (VBAT1 and VBAT2). Due to the internal pullup
resistor a leakage current of 3.3 V / 100 kΩ is expected. |
Pin36 | VBAT_RESET | - |
Pin37 | VBAT1 | Power | Power supply for the module, must be connected to battery (2.3
V to 3.6 V) |
Pin38 | GND | - | Ground |
Pin39 | NC | - | - |
Pin40 | VBAT2 | Power | Power supply for the module, must be connected to battery (2.3
V to 3.6 V) |
Pin41 | NC | - | - |
Pin42 | GPIO30 | | GPIO |
Pin43 | GND | | Ground |
Pin44 | GPIO30 | | |
Pin45 | NC | - | - |
Pin46 | GPIO1 | I/O | GPIO |
Pin47 | GPIO2 | I/O | GPIO |
Pin48 | GPIO3 | I/O | GPIO |
Pin49 | GPIO4 | I/O | GPIO |
Pin50 | GPIO5 | I/O | GPIO |
Pin51 | GPIO6 | I/O | GPIO |
Pin52 | GPIO7 | I/O | GPIO |
Pin53 | GPIO8 | I/O | GPIO |
Pin54 | GPIO9 | I/O | GPIO |
Pin55 | GND | - | Thermal ground |
Pin56 | GND | - | Thermal ground |
Pin57 | GND | - | Thermal ground |
Pin58 | GND | - | Thermal ground |
Pin59 | GND | - | Thermal ground |
Pin60 | GND | - | Thermal ground |
Pin61 | GND | - | Thermal ground |
Pin62 | GND | - | Thermal ground |
Pin63 | GND | - | Thermal ground |